Digital communication receivers typically must sample an incoming waveform and then reliably detect the sampled data. Typically, a receiver includes a Clock and Data Recovery (CDR) system to recover the clock and data from an incoming data stream. The CDR system generates a clock signal having the same frequency and varying phase as the incoming signal, which is then used to sample the received signal and detect the transmitted data.
CDR systems often employ well-known multiple stage proportional-integral (PI) digital loop filters, typically having multiple integrators in series. In a second order filter, for example, the first integrator includes a proportional register (PREG), and the second integrator includes an integral register (IREG), in a known manner. The CDR system recovers or locks to an initially unknown phase offset and frequency offset present in the incoming signal The integral state of the loop is directly related to the frequency offset The integral register is typically initialized to a value of zero (0) and the integral register value will eventually converge to a value that is proportional to the frequency of offset.
When a CDR is in a locked state, the sampling latches see a time stationary NRZ signal As a result, the Decision Feedback Equalization (DFE) eye opening can be calculated by comparing (for example, using an exclusive-or operation (XOR)) the decision latch output with the output of a vertical roaming latch, constrained with N-previous bits. See, fox example, U.S. patent application Ser. No. 11/540,946, filed Sep. 29, 2006, entitled “Method And Apparatus For Determining Latch Position For Decision-Feedback Equalization Using Single-Sided Eye,” for a discussion of DFE eyes. If the CDR loses the locked state, however, the NRZ signal is not time stationary. The CDR will start to diverge from the sampling clocks. When a CDR is out of lock, the CDR loop may build up the wrong values for the integral and proportional registers (IREG and PREG) Conventional techniques have used integral register (IREG) or proportional register (PREG) variability as an indication of CDR loss detection. Such conventional techniques, however, may confuse integral or proportional register variability with actual parts-pet-million (ppm) deviation
A need exists for methods and apparatus for detecting a loss of lock condition in a clock and data recovery system. A further need exists for methods and apparatus that take corrective action to restore a locked condition in a clock and data recovery system.